FIG. 4 is a diagram showing an example of a typical configuration of a clock and data recovery circuit. As regard to the clock and data recovery circuit, a description in Patent Document 1 is referred to. Referring to FIG. 4, this clock and data recovery circuit receives an input data signal and includes N latch circuits 102 (constituted from F/F1 to F/FN) for sampling the input data signal in response to a multi-phase clock signal (constituted from N-phase clocks CK1 to CKN), respectively, from a phase shift circuit 101, and for outputting sampled signal, a phase comparison circuit 103 for receiving outputs from the N latch circuits 102, for phase comparison, and outputting an up/down signal based on a result of the comparison, a filter 104 for smoothing an output of the phase comparison circuit 103, an up/down counter 105 for receiving the up/down signal smoothed by the filter 104, and performing counting up and counting down when the up/down signal indicates an up operation and a down operation, respectively, and a phase shift circuit 101 for receiving a phase control signal from the up/down counter 105 and performing control to advance or delay phases of the N-phase clock signals. The N-phase clock signals generated by dividing a reference clock signal from a PLL circuit not shown by a frequency divider circuit not shown are supplied to the phase shift circuit 101. The phase shift circuit 101 is constituted from a phase interpolator for changing the phases of the input N-phase clock signals according to the phase control signal.
The input data signal is sampled by the latch circuits 102 (constituted from the F/F1 to F/FN) in response to the N-phase clock signals. To the odd-numbered F/Fs, the clock signals each of which has a rising (or falling) edge in the vicinity of a center of a data settlement period are supplied, as clock signals for data sampling each for sampling the input data signal. To the even-numbered F/Fs, the clock signals each of which has a rising (or falling) edge in the vicinity of a point of change in data are supplied, as clock signals for edge detection each for detecting a transition point of the input data. Respective data sampled by the F/F1 to F/FN are supplied to the phase comparison circuit 103. The data sampled by the odd-numbered F/Fs are output as output data. The phase comparison circuit 103 compares the data sampled in mutually adjacent phases, thereby determining the point of change of the input data. When the phase of the clock signal lags behind the phase of the input data signal, the phase comparison circuit 103 outputs the up signal. When the phase of the clock signal leads the phase of the input data signal, the phase comparison circuit 103 outputs the down signal.
The filter 104 receives the up/down signal output from the phase comparison circuit 103 to generate the smoothed up/down signal by a majority decision circuit or the like.
The up/down counter 105 generates the phase control signal for the phase shift circuit 101 so that when the up/down counter 105 receives the up signal from the filter 104, the up/down counter 105 makes the phases of the N-phase clock signals CK1 to CKN “up” (advances the phases of the clock signals CK1 to CKN relative to the phase of the input data signal), and when the up/down counter 105 receives the down signal from the filter 104, the up/down counter 105 makes the phases of the clock signals “down” (the phases of the clock signals CK1 to CKN are delayed relative to the phase of the input data signal).
The phase control signal output from the up/down counter 105 to the phase shift circuit 101 is made common to the clock signals for data sampling the input data and the clock signals for edge detection at the latch circuits 102. That is, delays and advances in the phases of the N-phase clock signals CK1, CK2, CKN-1, and CKN from the phase shift circuit 101 (with the phases of the mutually adjacent clock signals spaced to each other by 360/N degrees) are controlled in common.
Generally, in a locked state (in the state where the phase of each of the clock signals for data sampling is located in the vicinity of the center of a data bit determination period) of the clock and data recovery circuit, the phase of each of the clock signals for detecting the transition (edge) of the input data signal is controlled to repeat going up and down around the point of the change of the input data signal.
As described above, the clock signal data recovery circuit shown in FIG. 4 is configured to phase shift all of the multi-phase clocks in unison at equal intervals. That is, as shown in FIG. 5 as a timing waveform diagram, the clock signals for edge detection each for detecting the transition point of the input data and the data sampling clock signal for sampling the input data at a data determination point are controlled by the common phase control signal. Accordingly, when an edge of one of the clock signals for edge detection (refer to an arrow mark in FIG. 5) changes, an edge of one of the clock signals for data sampling (refer to an arrow mark in FIG. 5) changes with the same phase as that of this signal. That is, when edge detection and data bit content are sampled by the latch circuits 102 in FIG. 4 using the clock signals of two phases and when the transition point of the data is delayed in a certain cycle due to jitter of the input data signal or like, the transition point of the data may come earlier in the subsequent cycle (with a period of the cycle reduced). In this case, when the edge detecting clock signal and the data sampling clock signal are delayed by the same phase, incorrect sampling of a data bit such as sampling of a transition region of the subsequent cycle (a data bit boundary) as the data bit may be performed (as described in Patent Document 2).
Patent Document 2 proposes a clock and data recovery circuit that controls the clock signals for data sampling and the clock signals for edge detection for input data separately, as shown in FIG. 6, as the clock and data recovery circuit that has suppressed an influence caused by a jitter component and has enabled correct data sampling. Referring to FIG. 6, component arrangement and the like of FIG. 6 are slightly different from a configuration described in a drawing in Patent Document 2 so as to obtain correspondence with FIG. 4. However, a basic configuration of FIG. 6 is the same as that in Patent Document 2. Referring to FIG. 6, this clock and data recovery circuit includes a control circuit 106 between the up/down counter 105 and the phase shift circuit 101 in the configuration in FIG. 4. The control circuit outputs two phase control signals for respectively controlling the clock signals for data sampling (odd-numbered clock signals) and the clock signals for edge detection (even-numbered clock signals) for input data separately.                [Patent Document 1]                    Japanese Patent Kokai Publication No. JP-P2002-190724A                        [Patent Document 2]                    Japanese Patent Kokai Publication No. JP-P2003-333021A                        [Non-patent Document 1]                    ISSCC 1993 p.p. 160-161 Mark Horowitz et al., “PLL Design for 500 MB/s Interface”                        